1. Field of the Invention
Embodiments presented herein relate generally to computing systems, and, more particularly, to a method for receiver enable cycle training for double data rate (DDR) memory.
2. Description of Related Art
Electrical circuits and devices that execute instructions and process data have evolved becoming faster and more complex. With the increased speed and complexity of electrical circuits and data processors, DDR memory training has become more problematic, particularly for receiver enable cycle training. As technologies for electrical circuits and processing devices have progressed, there has developed a greater need for efficiency, reliability and stability, particularly in the area of DDR memory receiver enable training. However, considerations for algorithm processing, overall system boot-up performance, as well as system complexity introduce substantial barriers to efficiently training receiver enable cycles in DDR memory systems. The areas of training to the correct cycle and training to the correct phase, variances in hardware such as processor die, processor packages, memory bus layout and memory itself are particularly problematic, for example, in systems that utilize and/or support different types of interchangeable microprocessors or DDR RAM such as dynamic RAM (DRAM).
Typically, modern implementations for receiver enable cycle in DDR systems, as noted above, have taken the approach of solving these training issues in one of two ways. One way is to allow a computer system's basic input/output system (BIOS) to train the receiver enable (RxEn) delay after comparing a series of memory write and read cycles. However, this approach has undesirable drawbacks. For example, this approach relies upon simple data patterns in order to infer the data strobe position and thus cannot adequately compensate for signaling effects such as data strobe jitter which leads to undesired RxEn settings. This approach is also very time consuming. A second approach uses a hardware phase recovery engine (PRE) in conjunction with a software algorithm to sample the signal phase over a number of data strobe pulses driven by the DRAM in response to a series of host controller read commands. This second approach, however, relies upon an input such as an estimate of the actual RxEn cycle and phase delay for the configuration (e.g., an RxEn seed). That is, the RxEn seed must be within a theoretical plus-or-minus (“±”) one-half of the memory clock range of the actual value for the RxEn delay to be trained successfully. If the RxEn seed is outside of the required range, the training result aliases to an incorrect RxEn cycle because the incoming data strobe pulses are periodic. With an improper RxEn cycle, subsequent read data transfers would be framed incorrectly and be corrupted.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.